Class 05: Device Physics II


 Jodie Ward
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1 Topics: 1. Introduction 2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor  Band Diagrams at V=0 6. NFET as a Capacitor  Accumulation V<0 7. NFET as a Capacitor  Depletion V>0 8. NFET as a Capacitor  Inversion V>>0 9. Band Diagrams, Charges, EField, and Potential 10. Band Diagrams at various biasing 11. Depletion Layer Width vs. Substrate Doping 12. NFET Cross Section, Parasitics, and Biasing 13. Full CV Curve for reference 1
2 NFET Model and Cross Section with Parasitics (Martin p.101) Goal is to understand the parasitic regions and terms shown in the model and cross section Last lecture covered the pn junctions of the source and drain This lecture will cover the channel Question  where is the biggest capacitor? 2
3 NFET as a Capacitor (Martin p.87, Singh p.418) The channel region of an FET can be thought of as a series connection of capacitors, the capacitance due to the thin oxide, and the capacitance due to the semiconductor. The thin oxide capacitance is fixed. The semiconductor capacitance depends on the biasing 3
4 Capacitance vs. Voltage Curves (Singh p.419) Much like IV curves define a transistor, CV curves define capacitors Three regions of importance: (1) accumulation (2) depletion (3) inversion Further foils will describe each of these regions Once again, this is the channel region of a transistor and how it behaves when biased To obtain a CV curve, one biases the top plate with a DC bias, and uses an AC signal to determine the response of the carriers at the surface to the AC signal. So from I=C dv/dt, one can back out the capacitance based on the measured current 4
5 NFET as a Capacitor  Band Diagrams at V=0 (Sze p.427) This state is referred to as the flatband condition that is, no applied potential, the bands are flat in the ideal case. So why is Vfb not at Vg=0 in the CV plot below? Important terms to take from these diagrams are: d insulator thickness qψ B Energy of offset between Fermi and intrinsic levels Important observations to make: How can you tell from the band diagram which is ntype and which is ptype semiconductor? Even the oxide has bands of allowed states, it is just that the band gap is very large This portion of CV curve referred to as the flat band capacitance 5
6 NFET as a Capacitor  Accumulation V<0 (Sze p.428; Martin p.89; Mason) This state is referred to as the accumulation condition that is, where the majority carriers are accumulated at the surface Important observations to make: With a parallel plate analogy, this is where the total capacitance is due to the Cox and Cs is zero Accumulation: In accumulation, charges are separated by the gate oxide so we can write the gate capacitance per unit area as C G = C OX = ε OX / t OX where ε OX is the permittivity of the oxide (= 3.9 ε 0 ), and t OX is the thickness of the oxide. The total capacitance would be multiplied by the area of the gate which is the product of the width, W, and length, L, of the gate (A=W*L). 6
7 NFET as a Capacitor  Depletion V>0 (Sze p.428; Martin p.89) This state is referred to as the depletion condition because the majority carrier are depleted from the surface Important observations to make: With a parallel plate analogy, this is where the thickness of the Cs plate is increasing, due to the increase in the depletion regions. Thus the capacitance is going down. C G = C OX C dep / (C OX + C dep ) < C OX 7
8 NFET as a Capacitor  Inversion V>>0 (Sze p.428; Martin p.89) This state is referred to as the inversion condition because the minority carriers are brought to the surface of the channel. However, minority carrier respond slower to the AC signal (minority carrier lifetimes). Thus inversion in a CV curve is only obtained with very slow varying signals. Important observations to make: With a parallel plate analogy, this is where the thickness of the Cs plate is at its maximum. During normal operation of a transistor, the carriers are supplied by the source and drain, so there is no lack of carriers. The definition of inversion is where surface potential > bulk potential Vt is defined as the condition in which the surface is inverted, based on Cmi 8
9 Band Diagrams, Charges, EField, and Potential (Sze p.434) Spice model parameter PHI is 2Ψ s 9
10 Band Diagrams at various biasing (Sze p.430) 10
11 Depletion Layer Width vs. Substrate Doping (Sze p.437) 11
12 NFET Cross Section, Parasitics, and Biasing (Martin p.101) We have covered the source/drain to substrate junctions, and now the gate/oxide/surface junction Next, how they come together for the operation of an NFET 12
13 Full CV Curve for reference (Sze p.438) 13
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